%0 Journal Article
%A Rao, M V Ganeswara, Kumar , P Ravi , Balaji, T 
%T A High Performance Dual Stage Face Detection Algorithm Implementation using FPGA Chip and DSP Processor
%J Journal of Information Systems and Telecommunication (JIST) 
%V 10
%N 40
%P 241-248
%D 2022
%R 10.52547/jist.31803.10.40.241
%U https://rimag.ir/fa/Article/31803